Semiconductor memory devices typically consist of a number of individual cells for storing data. In a conventional binary memory device, each cell can store one of two states to represent one bit of data. Alternatively, each memory cell might store more than one bit of data. Such memory devices are referred to as multi-level or multi-bit memory devices. Multi-level memory devices increase the storage capacity and density over conventional binary devices. For example, a memory device capable of storing two bits of data per cell has a capacity to store twice the data than can be stored in the same number of conventional binary memory device.
The programming of conventional binary memory devices consists of storing or programming one of two levels or states in a memory cell to represent all the possible values for one bit of data. For example, a conventional memory cell, when accessed during a write operation, stores a first voltage or threshold level to represent a first state and stores a second voltage or threshold level to represent the second state. In a multi-level memory device, however, typically one of n states is stored to represent more than a single bit of data. Although the ability to store a single bit requires the ability to store at least two levels as in the prior art binary memory cells, "multi-level" as used here is intended to refer to a cell capable of storing one of more than two levels or states (i.e., more than one binary digit), and "binary" refers to a cell capable of storing one of only two levels (i.e., one binary digit). For example, in order to store two bits in each multi-level memory cell, each cell must be capable of storing one of at least four levels. A multi-level cell capable of storing n bits, must be able to support 2.sup.n threshold levels because each bit can have one of two levels.
One type of multi-level memory cell is a flash multi-level memory cell. In general, flash memory cells include a floating gate field effect transistor. Each floating gate transistor has a select gate, a floating gate, a source, and a drain. Information is stored in the flash cell by altering the amount of charge stored on the floating gate. This in turn causes the threshold voltage, V.sub.t, of the floating gate field effect transistor to be varied. The typical prior art binary flash memory cell can be in one of two possible states, being either "programmed" or "erased". Theoretically, the flash cell possesses a distinct state for each electron that is added to the floating gate. Practically however, prior art flash cells have a limited number of states due to constraints including inconsistencies in flash cell structure, charge loss over time, and limitations in sensing the charge stored on the floating gate.
The actual charge stored on a programmed cell may vary from one programmed cell to another programmed cell or from one erased cell to another erased cell. In order to accommodate this factor, the binary flash cell is interpreted as storing a "1" if V.sub.t is within a first range of values and a "0" if V.sub.t is within a second range of values. The first and second ranges are distinct and may be separated by a "separation range". In other words, if the threshold voltage, V.sub.t, is programmed to a value within one set of values, the cell state is a "1". If the threshold voltage, V.sub.t, is programmed to a value within another set of values, the cell state is a "0". The difference between these sets of values is called the separation range.
When a flash cell is read, the current conducted by the flash cell is compared to a current conducted by a reference flash cell having a threshold voltage, V.sub.t, set to a predetermined voltage that lies within the separation range. When a flash cell is selected for reading, a biasing voltage is applied to the select gate of the field effect transistor. Simultaneously, the same biasing voltage is applied to the select gate of the reference cell. If the flash cell is "programmed," excess electrons are trapped on the floating gate, and the threshold voltage, V.sub.t of the flash cell has increased such that the selected flash cell conducts less drain current than the reference flash cell. The programmed state of the prior art binary flash cell is typically associated with a logic 0. If the prior art flash cell is "erased", the floating gate has fewer electrons and the flash cell conducts more drain-to-source current than the reference cell. The erased state of the prior art binary flash cell is usually associated with a logic 1.
Multi-level flash cells are capable of storing one of more than two levels. For example, a multi-level flash cell capable of storing 2 bits can be placed into one of four states. This means that one state is uniquely assigned to one of the four possible combinations of two bits, "00," "01," "10," and "11." 2.sup.n -1 references are required to distinguish between 2.sup.n states. Thus for 4 states, there must be 3 reference voltages and 3 separation ranges. For comparison, the prior art binary flash cell typically uses one reference voltage to distinguish between 2 states.
These multi-level flash cells are read by comparing each of the 2.sup.n -1 voltage references to a voltage determined by the drain-to-source current of the memory cell. Decoding logic is then used to translate the output of the 2.sup.n -1 comparators into n bits.
A flash memory device typically includes arrays of flash memory cells. These arrays are typically grouped into or further subdivided into blocks. Prior art flash memory can be programmed cell by cell, however, flash memory can only be erased in blocks of cells.
One disadvantage of the prior art write technique is that once a block has data written to it, the data in that block cannot be modified without erasing the block first. In other words, the prior art write techniques permit only one write cycle for every erase cycle.
One application of flash memory is in the area of solid state "disks". Solid state disks use nonvolatile memory, such as flash memory, to emulate a conventional computer disk storage device. Typically, disk sectors are mapped either physically or logically onto blocks of flash memory cells. Because only one write cycle is possible for each erase cycle in the prior art storage systems a method of "cleaning up" the previously written to cells is necessary in order to make those cells available for data storage again. Typically, the valid data in a block is copied with the updated data to another block location. Then the previous block location is marked for cleanup. The cleanup process erases the entire block and makes the block available for storage again.
One disadvantage of the prior art method of one write for each erase on the cell is the amount of energy consumption required. Thus in applications where the stored data must be modified frequently, considerable amounts of energy are consumed in moving the valid data to a new location and erasing the blocks that the information was previously stored in.
Another disadvantage of performing an erase step in order to reprogram the cells is that the erase process typically takes considerably longer to execute than the programming process.
Another disadvantage of an erase for every programming cycle are the cycling induced reliability errors. The flash memory cells deteriorate with each program/erase cycle.